1. Field of Invention
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of adjusting the impedance of a data output driver.
2. Description of Prior Art
Dynamic random access memory (DRAM) has been improved continuously to increase its operational speed. Synchronizing an internal clock signal with an external clock signal is one of the methods used to improve an operational speed of the DRAM. A DRAM which is operated in synchronization with the external clock signal is called a synchronous dynamic random access memory (SDRAM). The SDRAM performs a data access operation at a rising edge of the external clock signal. Thus, the SDRAM can perform data access operations once per cycle of the external clock signal. An SDRAM that performs data access operations once per external clock signal is often referred to as a single data rate (SDR) SDRAM.
The SDR SDRAM has been improved for use in a high speed system. The double data rate (DDR) SDRAM performs data access operations at both a rising edge and a falling edge of the external clock signal. In other words, the DDR SDRAM performs data access operations twice per external clock signal. A double data rate 2 (DDR2) SDRAM is an upgraded version of the DDR SDRAM.
For enhancing operational speed of the DDR2 SDRAM, new concepts have been described by an international electronics standardization organization, namely the Joint Electron Device Engineering Council (JEDEC). An off chip driver (OCD) calibration control is one such new concept. The OCD calibration control allows adjusting the impedance of a data output driver to an optimum value. The optimum impedance of the data output driver can be found by measuring a current flow from an external device, such as a chipset, to the data output driver, or a voltage between the chipset and the data output driver.
FIG. 1 is a block diagram showing a data interface between a chipset and a conventional DDR SDRAM. The data interface shown in FIG. 1 illustrates how data access operations are performed. As shown, the DDR SDRAM receives a plurality of command signals such as a chip selection bar signal/CS, a write enable bar signal/WE, a clock signal CLK and a clock bar signal/CLK from the chipset. The conventional DDR SDRAM also receives a plurality of address signals A0 to A15. In addition, the conventional DDR SDRAM receives or outputs data through a plurality of data output pins DQ0 to DQ15.
The DDR SDRAM receives a data strobe signal DQS through a data strobe input pin DQS. The data strobe signal DQS periodically changes its logic level while the data access operation is performed. The DDR SDRAM generally uses the data strobe signal DQS for aligning and transfers the aligned data to the inside of the DDR SDRAM.
FIG. 2 is a flow chart showing an operational procedure of performing an OCD calibration control operation introduced by the JEDEC. Each step of the operational procedure is marked by step numbers from 10 to 21. The operational procedure can be considered as having two sequences—a first sequence for measuring impedance of the data output driver and a second sequence for adjusting the impedance.
The data output driver includes a pull-up driver and a pull-down driver, and activates one of those drivers to output data. That is, the data output driver outputs data having a logic high level through the pull-up driver and outputs a data having a logic low level through the pull-down driver. Therefore, the impedance of the data output driver can be measured by measuring the impedance of the pull-up driver or the impedance of the pull-down driver. In a first drive mode DRIVE1, the impedance of the pull-up driver is measured and, in a second drive mode DRIVE0, the impedance of the pull-down driver is measured.
The operational sequence of performing the OCD calibration control operation is described below referring to FIG. 2. If a drive mode is set to the first drive mode DRIVE1 by an extended mode register set (EMRS), data signals outputted through all data pins (DQ pins) and the data strobe signal DQS become a logic high level, and the data strobe bar signal/DQS becomes a logic low level as shown in the step 10. Various operations of a DDR SDRAM are controlled based on a value set in the EMRS. Herein, in the first drive mode DRIVE1, the impedance of the data output driver is measured when the pull-up driver outputs the data as a logic high level.
Then, the chipset measures the impedance of the pull-up driver. If the measured impedance of the pull-up driver is an optimum value for a current system status, the EMRS is set as a termination of the OCD calibration control operation, as shown in the steps 11 and 15. After the step 15, the OCD calibration control operation is performed again, i.e., the EMRS is set as the second drive mode DRIVE0 as shown in the step 16. Otherwise, if the measured impedance of the pull-up driver is not the optimum value for the current system status, the EMRS is set as an adjustment mode for adjusting the measured impedance of the pull-up driver as shown in the steps 11 and 12.
In the adjustment mode, referring to the steps 13 and 14, the output impedance of the pull-up driver is increased or decreased by decoding a burst code to thereby adjust the impedance of the pull-up driver. The burst code is outputted by the chipset and a burst length (BL) is set to 4. In the adjustment mode, the output impedance of the pull-up driver is adjusted by controlling the number of turned-on pull-up MOS transistors included in the pull-up driver. The pull-up MOS transistors are connected in parallel and, also, each of the pull-up MOS transistors has a same driving strength.
Thereafter, the OCD calibration control operation is terminated based on the EMRS as shown in the step 14. Then, the OCD calibration control operation is performed again, i.e., the EMRS is set as the first drive mode DRIVE1 for measuring the impedance of the pull-up driver again as shown in the step 10.
If the impedance of the pull-up driver is not the optimum value, the impedance of the pull-up driver is adjusted by the same way, i.e., the steps 12 to 14, described above until the measured impedance is considered as the optimum value. If the impedance of the pull-up driver is the optimum value, the drive mode, i.e., a value set in the EMRS, is set to the second drive mode DRIVE0 as described above at the step 16. In the second drive mode DRIVE0, the impedance of the data output driver is measured when the pull-down driver outputs the data having a logic low level to the chipset. That is, the chipset measures the impedance of the pull-down driver. If the measured impedance of the pull-down driver is an optimum value for the current system status, the OCD calibration control operation is terminated as shown in the steps 17 and 21.
On the other hand, if the measured impedance of the pull-down driver is not the optimum value for the current system status, the EMRS sets the adjustment mode for adjusting the measured impedance of the pull-down driver as shown in the step 18. Then, the steps 19, 20, 16 and 17 are sequentially performed until the measured impedance of the pull-down driver becomes the optimum value. If the measured impedance of the pull-down driver becomes the optimum value as a result of the step 17, the OCD calibration control operation is terminated at the step 21.
FIG. 3A is a timing diagram showing the operation of measuring the impedance of the data output driver while the OCD calibration control operation is performed. FIG. 3B is an operation table showing an operation of performing the OCD calibration control operation in response to a 3-bit control signal inputted through address pins A7, A8 and A9. The operation for measuring the output impedance of the data output driver is described in detail referring to FIGS. 3A and 3B.
First, the chipset inputs the 3-bit control signal to a DDR2 SDRAM so that the EMRS can set the drive mode to one of the first drive mode DRIVE1 and the second driver mode DRIVE0. The 3-bit control signal is inputted to the address pins A7 to A9. The OCD calibration control operation according to the 3-bit control signal is defined in the operation table shown in FIG. 3B. For example, if the 3-bit control signal is 100 or 010, the EMRS sets the drive mode to the first drive mode DRIVE1 or the second drive mode DRIVE0 respectively. After that, if the 3-bit control signal is 001, the EMRS sets the adjustment mode. In addition, if the 3-bit control signal is 111, the impedance of the data output driver is set to a default impedance value.
In the first drive mode DRIVE1, the data output driver outputs the data as a logic high level through the pull-up driver and the impedance of the pull-up driver is measured. In the second drive mode DRIVE0, the data output driver outputs the data as a logic low level through the pull-down driver and the impedance of the pull-down driver is measured. The ‘EMRS’ shown in FIG. 3A indicates a timing of setting the EMRS and the ‘NOP’ means no-operation.
FIG. 4A is a timing diagram showing an operation of adjusting the impedance of the data output driver while the OCD calibration control operation is performed. FIG. 4B is an operation table showing the OCD calibration control operation according to the burst code. The operation of adjusting the impedance of the data output driver is described in detail referring to FIGS. 4A and 4B.
If the EMRS sets the adjustment mode, the chipset inputs the 4-bit burst code to the conventional DDR SDRAM through the DQ pins. The operation table shown in FIG. 4B shows the operation in the adjustment mode according to the 4-bit burst code. The operation in the adjust mode is performed by turning on/off MOS transistors included in the data output driver as described above. For example, if the burst code is inputted as ‘1000’ once, one of activated pull-down MOS transistors included in the pull-down driver is turned-off. If the burst code is inputted as ‘1001’, the number of activated pull-up MOS transistors included in the pull-up driver is increased by one and the number of activated pull-down MOS transistors included in the pull-down driver is decreased by one. After the adjustment mode is completed, i.e., the 3-bit control signal is inputted as ‘000’, the OCD calibration control operation is finished.
The above-described OCD calibration control operation is a newly introduced concept by the JEDEC and a circuit for performing the OCD calibration control operations has not been developed yet. Therefore, an electronic circuit capable of performing the OCD calibration control operation is desired for a DDR2 SDRAM.